Electronic Design

Use Hybrid PMOS-NMOS Active Loads To Cut Substrate Noise In Differential Amplifiers

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...
Semiconductor Engineering

Speeding Up NMOS

For years—decades, in fact—the NMOS transistor world has been on cruise control. NMOS is naturally faster and its performance has scaled better than PMOS. PMOS has had a cost advantage. But lately, it ...
sciencex

Towards a process flow for monolithic CFET transistor architectures

—The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and ...
Nature

P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors

The Nature Index 2024 Research Leaders — previously known as Annual Tables — reveal the leading institutions and countries/territories in the natural and health sciences, according to their output in ...
EDN

Additional structures in analog layout beyond schematic

A schematic diagram is not a detailed blueprint of an analog circuit; instead, it’s more like architectural sketch of the circuit. Look at any schematic for a CMOS analog IC circuit and you will see ...
Semiconductor Engineering

Mobility Gets A Boost With Expanded Epi Applications

Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of ...
Electronic Design

Intel Proposes New Path for Moore's Law With 3D Stacked Transistors

Intel CEO Pat Gelsinger has announced plans to recover the company's chip-making crown by 2025. But the company has shared more details about research that could help it compete even further in the ...